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R8A66156SP
24-bit I/O EXPANDER WITH LED DRIVE FUNCTION
REJ03F0283-0100 Rev. 1.00 Sep.14.2009
DESCRIPTION
R8A66156 is a semiconductor integrated circuit which has 24-bit shift register function to execute serial in parallel out conversion and parallel in - serial out conversion. Built in two shift registers for serial in - parallel out and parallel in - serial out are constructed independently, This IC is able to read serial input data into a shift register while output the serial data converting from the parallel data input. Also, parallel data I/O pins can be set to input mode or output mode by a bit. R8A66156 is useful in a wide range of applications, such as MCU (micro controller unit) I/O port extension and serial bus system data communication. Moreover, R8A66156 can be used as the anode common LED drive too.
FEATURES
Bi-directional serial communication with MCU Serial data can be input during parallel to serial data conversion Parallel data I/O pins can be set input mode or output mode by a bit Schmitt input (DI, CLK, /S, /CS) N-ch open drain output (DO, D1~D24) High output current IOL=24mA (at VCC=4.5V), IOL=15mA (at VCC=3.0V) Parallel data I/O pins (D1~D24) Wide supply voltage range (Vcc=2.0 to 6.0V) Wide operating temperature range (Ta=-40 to 85)
APPLICATION
Serial - parallel or parallel - serial data conversion for MCU peripheral. Serial bus control by MCU. LED array drive, The various LED display modules.
PIN CONFIGURATION (TOP VIEW)
GND SERIAL DATA OUTPUT DO SERIAL DATA INPUT DI Vcc CLOCK INPUT CLK GND CHIP SELECT INPUT CS Vcc SET INPUT S GND D24 D23 D22 PARALLEL DATA I/O D21 D20 D19 D18 D17 D1 D2 D3 D4 D5 D6 D7 D8 GND D9 D10 D11 D12 D13 D14 D15 D16 GND PARALLEL DATA I/O PARALLEL DATA I/O
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
REJ03F0283-0100 Rev.1.00 Sep.14.2009 Page 1 of 7
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R8A66156SP
BLOCK DIAGRAM
Vcc
4
Vcc
8 2 DO
Vcc
Shift register 1 DO D24 D23 D22 D3 D2 D1 Control circuit CLK 5 S CS
9 7
CLK, S, CS, DI
36 D1 35 D2 34 D3
S
Input type
13 D22 12 D23 11 D24
Vcc
Vcc
Q24 Q23 Q22 Q3 Q2 Q1 Parallel output latch D24 D23 D22 D3 D2 D1 Q24 Q23 Q22 Q3 Q2 Q1 Shift register 2 DI DI 3
1 6 10 19 28
DO
D1D24
Output
GND GND GND GND GND
Inout Output Type
FUNCTION
The R8A66156 is produced by using the silicon gate CMOS technology and has low power dissipation and high noise margin. Built in two shift registers for serial in-parallel out (Shift register 2) and parallel in-serial out (Shift register 1) are constructed independently, R8A66156 is able to read serial input data into a shift register while output the serial data converting from the parallel data input. Serial output operation of 24-bit parallel latched data and serial input operation from MCU are started when /CS is changed from "H" to "L". 24-bit parallel data are latched by the negative edge of /CS and are output from the DO terminal synchronously to the negative edge of CLK, and also the DI terminal read serial input data from MCU and are written into the internal shift register 2. The 25th and following shift clock pulse are ignored and serial input data is masked, and DO terminal becomes high-impedance ("High-Z"). When /CS is changed from "L" to "H", 24-bit serial data which is read from the DI terminal are output to the D1~D24 terminals as parallel data. As the output circuit type of D1~D24 terminals is N-ch open drain output, write data "H" for pins which should be set to input mode.
REJ03F0283-0100 Rev.1.00 Sep.14.2009 Page 2 of 7
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R8A66156SP
DESCRIPTION OF OPERATION
(1) When power ON, the status of DO and D1~D24 terminals are not determined. These terminals are turn to high-impedance when "L" is input to the /S terminal. (2) By the negative edge of /CS, the status of D1~D24 terminals is loaded on shift register 1. (3) Synchronous to the negative edge of CLK, 24-bit loaded data is serial output from the DO terminal. (4) Synchronous to the positive edge of CLK, 24-bit serial input data from DI is write into the shift register 2. (5) The 25th and following shift clock pulse are ignored and the serial data input operation is stopped. And the DO terminal becomes high-impedance ("High-Z"). (6) By the positive edge of /CS, input data described in (4) is output to D1~D24 terminals. (7) Shift register 1 loads the AND tie data of external parallel input data and latched data on parallel output latch. (8) If the /CS is changed from "L" to "H" before reaches the 24th bit of CLK, parallel output latch latches data which has been written on shift register 2 and output it to D1~D24 terminals. Serial data after this since is ignored and the DO terminal becomes high-impedance. (9) Input/output mode set to D1~D24 terminals is done by the serial input data to the DI terminal. Terminals which "H" is written are set to input, and "L" is written are set to output.
OPERATION TIMING CHART
S (1)
CS
(2) 1 2 3 4 5 6 7 8 9 10 23 24 25 (5)
CLK (4) DI
High-Z DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 DO9 DO23 DO24 High-Z
(3) DO
DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DI9 DI23 DI24
(6) D1
High-Z DI1 DO1
D2
High-Z
DI2
DO2
D24
High-Z DI24 DO24
1 Sequence
REJ03F0283-0100 Rev.1.00 Sep.14.2009 Page 3 of 7
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R8A66156SP
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO IO ICC Pd Tstg Parameter Supply voltage Input voltage Output voltage Output current per output pin Supply / GND current Power dissipation Storage temperature range VCC, GND (Note)
(Ta=-40~85, unless otherwise noted) Conditions Ratings -0.5 ~ +7.0 -0.5 ~ Vcc+0.5 -0.5 ~ Vcc+0.5 50 630 700 -65 ~ 150 Unit V V V mA mA mW
RECOMMENDED OPERATING CONDITIONS
Symbol Vcc VI VO Topr Parameter Supply voltage Input voltage Output voltage Operating temperature range Limits Min. 2.0 0 0 -40 Typ. Max. 6.0 Vcc Vcc 85 Unit V V V
ELECTRICAL CHARACTERISTICS
Symbol VT+ VTVIH VIL VOL Parameter Positive going threshold voltage (*1) Negative going threshold voltage (*1) "H" input voltage (*2) "L" input voltage (*2) "L" output voltage
(Vcc=2.0~6.0V, Ta=-40~85, unless otherwise noted) Test conditions Min. 0.35 x Vcc Limits Typ. Max. 0.80 x Vcc 0.65 x Vcc 0.25 x Vcc Unit V V V V V V V uA uA uA
Vo=0.1V, Vcc-0.1V l Io l=20uA
0.20 x Vcc 0.75 x Vcc
VI=VT+,VTVcc=4.5V VI=VT+,VTVcc=3.0V VI=VT+,VTVcc=2.0V
IOL=24mA IOL=15mA IOL= 8mA
0.5 0.5 0.3 10 -10 1 -1 100
IO IIH IIL Icc
Output leakage current "H" input current "L" input current Quiescent supply current
Vo=Vcc Vo=GND VI=Vcc, Vcc=6V VI=GND, Vcc=6V VI=Vcc, GND Vcc=6V Vcc=6V
*1 : DI, CLK, /CS, /S *2 : D1~D24
REJ03F0283-0100 Rev.1.00 Sep.14.2009 Page 4 of 7
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R8A66156SP
SWITCHING CHARACTERISTICS
Symbol fmax tPLZ tPZL tPLZ tPZL tPLZ Parameter Maximum repeat frequency Output "L-Z" and "Z-L" propagation time CLK - DO Output "L-Z" and "Z-L" propagation time /CS - D1~D24 Output "L-Z" propagation time /S - DO, /S - D1~D24
(Vcc=2.0~6.0V, Ta=-40~85, unless otherwise noted) Test conditions Min. Limits Typ. Max. 1.9 400 400 400 400 400 Unit MHz ns ns ns ns ns
CL=50pF RL=1k (note1)
TIMING REQUIREMENTS
Symbol tw tsu Parameter CLK, /CS, /S pulse width Setup time of DI to CLK Setup time of /CS to CLK Setup time of D1~D24 to /CS Hold time of DI to CLK Hold time of /CS to CLK Hold time of D1~D24 to /CS Recovery time of /CS to /S
(Vcc=2.0~6.0V, Ta=-40~85, unless otherwise noted) Test conditions Min. 260 130 130 130 130 130 130 130 Limits Typ. Max. Unit ns ns ns ns ns ns ns ns
th trec
NOTE1: TEST CIRCUIT
(1) The pulse generator (P.G.) has the following characteristics (10%~90%) tr=6ns, tf=6ns, Zo=50 (2) The capacitance CL includes stray wiring capacitance and the probe input capacitance.
Input
Vcc
Vcc
RL
P.G.
50
DUT
CL
DO, D1D24
GND
REJ03F0283-0100 Rev.1.00 Sep.14.2009 Page 5 of 7
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R8A66156SP
TIMING DIAGRAM
tw tw
CLK
50% tPLZ
50%
50% tPZL
CS
50% tsu th
50%
DO
50% 10%
CLK
50%
50%
tw
tw
CS
50% tPLZ
50%
50% tPZL
S
50% trec
D1D24
50% 10%
CS
50%
tw
S
50% tPLZ
50%
DO, D1D24
10%
DI
50% tsu th
50%
CLK
50%
D1D24
50% tsu th
50%
CS
50%
REJ03F0283-0100 Rev.1.00 Sep.14.2009 Page 6 of 7
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R8A66156SP
PACKAGE OUTLINE
Package 36pin SSOP RENESAS Code PRSP0036GC-A Previous Code 36P2X-B
All trademarks and registered trademarks are the property of their respective owners.
REJ03F0283-0100 Rev.1.00 Sep.14.2009 Page 7 of 7
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